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publication number s29pl-n_00 revision a amendment 1 issue date august 8, 2005 s29pl-n mirrorbit? flash family s29pl256n, s29pl127n, s29pl129n, 256/128/128 megabit (16/8/8 m x 16-bit) cmos 3.0 volt-only simultaneous read/write, page-mode flash memory advance information

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s29pl-n mirrorbit? flash family s29pl256n, s29pl127n, s29pl129n, 256/128/128 megabit (16/8/8 m x 16-bit) cmos 3.0 volt-only simultaneous read/write, page-mode flash memory data sheet advance information
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2 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information contents notice on data sheet designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 input/output descriptions and logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 connection diagrams/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 special handling instructions for fbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 vbh084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.1 connection diagram C s29pl256n mcp compatible package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2.2 physical dimensions C vbh084, 8.0 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.3 vbh064, 8 x 11.6 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 connection diagram C s29pl127n mcp compatible package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 connection diagram C s29pl129n mcp compatible package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4.3.3 physical dimensions C vbh064, 8 x 11.6 mm C s29pl-n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 mcp look-ahead connection diagram/physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.1 for all page mode mcps comprised of code flash + (p)sra m + data flash . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.2 56-pin tsop pinout, s29pl256n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4.3 56-pin tsop pinout, (s29pl127n and s29pl129n). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4.4 physical dimensions C ts/tsr 056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1.1 dual chip enable device description and operation (pl129n only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.1 non-page random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2.2 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.3 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.4 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4.1 single word programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4.2 write buffer programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4.3 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.4 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 7.4.5 erase suspend/erase resume commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.4.6 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4.7 accelerated program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.4.8 unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.5 simultaneous read/write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.7 hardware reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.8 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.1 lock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.4 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.6 advanced sector protection software examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.2 low v cc write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.7.3 write pulse glitch protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 3 advance information 8.7.4 power-up write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 9.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 factory secured silicon sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2 customer secured silicon se ctor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.3 secured silicon sector entry and exit command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.3 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.4 key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.5 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.6 v cc power up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 11.7 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.7.1 dc characteristics (v cc = 2.7 v to 3.6 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.7.2 dc characteristics (v cc = 2.7 v to 3.1 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 11.8 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.8.1 read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.8.2 read operation timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 11.8.3 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.8.4 erase/program timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.8.5 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 11.8.6 bga ball capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.1 common flash memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13 commonly used terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 14 revisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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6 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 1 ordering information
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ib.! 4,4 valid combinations v io range ( note 3 ) package type ( note 2 ) base ordering part number speed option package type, material, & temperature range model number packing ty p e 67 6<=/ =9!=9 k.!k! k,.!k, 99 9!6!8 * /: + 6>a8=0 0g29;h;9)::= ;h"$4 "$*,gk+ 67 :6>/ 67 :67/ =9!=9 k.!k! k,.!k, 99 9!6!8 * /: + 6>a8=0 0g29=h;9)::= =h"$4 "$*,gk+ 67 6<=/! 67 :67/ 67 :6>/ >9 , i9 9!6!8 * /: + 6>a8=0 9<=*1 + i: :=<a:7<0 !
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 7 advance information 2 input/output descriptions and logic symbols $ 6 :

figure 2.1 logic symbols C pl256n, pl129n, and pl127n table 2.1 input/output descriptions symbol type description ) a9
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67 :67 max +1 16 amax ?a0 wp#/acc reset# ce# oe# we# ry/by# v io (v ccq ) dq15 ? dq0 22 16 dq15 ? dq0 a21 ? a0 wp#/acc reset# ce1# oe# we# ry/by# ce2# ! ) 34
567,
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logic symbol C pl129n logic symbol C pl256n and pl127n
8 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 3 block diagram ! 9:;':<
) 3 4)-567,0)-56!8,0)!-56!=,0 56!=,><>!<>< v io v cc v ss state control command register pgm voltage generator v cc detector timer erase voltage generator input/output buffers sector switches chip enable output enable logic y-gating cell matrix address latch y-decoder x-decoder data latch reset# ry/by# (see note) a max ? a3 a2?a0 ce# we# dq15?dq0 v io oe# * /8 +
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 9 advance information 4 connection diagrams/physical dimensions b1 67 6<=/ 4.1 special handling instructions for fbga package #
,4
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$:<9n 4.2 vbh084, 8.0 x 11.6 mm /7!7+

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0
2?$ figure 4.1 connection diagram C 84-ball fine-pitch ball grid array (s29pl256n) a7 a3 a2 dq8 dq14 rfu rfu wp#/acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 rfu f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 ry/by# a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 rfu h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-v cc rfu dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu rfu rfu rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-v cc rfu rfu f-v ccq l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 rfu rfu rfu rfu rfu rfu rfu rfu a1 a10 m1 m10 nc nc nc nc reserved fo r future use legend
10 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information /7!7! %
d2$=6>/9>76?++74 figure 4.2 physical dimensions C 84-ball fine-pitch ball grid array (s29pl256n) 3339 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 084 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 84 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-a9, b10-l10, depopulated solder balls m2-m9, b1-l1) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 11 advance information 4.3 vbh064, 8 x 11.6 mm /7 7+

d(!) *+!e5&

0
2?$ figure 4.3 connection diagram C 64-ball fine-p itch ball grid array (s29pl127n) h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
12 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information /7 7!

d(!) *+!)5&

0
2?$ figure 4.4 connection diagram C 64-ball fine-pitch ball grid array (s29pl129n) h4 h5 h6 h7 h8 h2 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 h2 h 2 c6 c7 ce1# h3 oe# rfu dq0 c3 a7 a8 we# wp/acc rfu b5 b7 c8 a11 rfu rfu a15 a12 a19 a21 a13 a9 ce2# a14 a10 a16 rfu dq6 e6 rfu a20 g4 f4 e4 e5 d5 rst# rfu ry/by# a18 a17 dq1 rfu dq15 dq13 dq4 dq3 dq9 dq7 rfu v cc dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 dq8 v ss dq12 dq14 dq5 rfu dq11 dq2 l5 l6 rfu rfu a1 nc a10 nc m10 nc m1 nc h2 c4 d4 d6 reserved for future use no connection j4 j6 j7 j8 j9 j2 j3 k3 k4 k5 k6 k7 k8 legend j5
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 13 advance information /7 7 %
d2$=64/9>?++74d(!)*" figure 4.5 physical dimensions C 64-ball fine-pitch ball grid array (s29pl-n) 3330 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbh 064 jedec n/a 11.60 mm x 8.00 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. ball footprint e1 7.20 bsc. ball footprint md 12 row matrix size d direction me 10 row matrix size e direction n 64 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement (a2-9,b1-4,b7-10,c1-k1, depopulated solder balls m2-9,c10-k10,l1-4,l7-10, g5-6,f5-6) bottom view top view side view a1 corner a2 a 10 9 10 ml j k e c 0.05 (2x) (2x) c 0.05 a1 e d 7 ba c ed f hg 8 7 6 5 4 3 2 1 e d1 e1 se 7 b ca c m 0.15 0.08 m 6 0.10 c c 0.08 nx b sd a b c seating plane a1 corner index mark
14 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 4.4 mcp look-ahead connection diagram/physical dimensions /7/7+
55 &
%f&( 5f

% ! 1!1@*5;1 11ab; 1 *$1c><' $1!c><
$ figure 4.6 mcp look-ahead diagram j3 oe# c3 vss d2 rfu d3 a7 d7 a8 d6 we# d8 a11 c8 r-oe# c7 rfu c6 c6 c 6 c 6 f-v cc c4 rfu e9 a15 e8 a12 e7 a19 f9 f9 a21 f8 f8 a13 f7 f7 a9 h9 a16 h8 a24 h7 dq6 f6 f6 a20 f4 f4 a18 h4 h4 dq1 j9 rfu j8 dq15 j7 dq13 j6 dq4 j5 dq3 j4 dq9 e3 a6 e2 a3 f3 f3 a5 f2 f2 a2 h3 h3 vss h2 h2 a0 l3 l3 dq8 m2 a27 m3 a26 l8 l8 dq14 l7 l7 dq5 l6 l6 a25 l5 l5 dq11 l4 l4 dq2 m4 vss rfu c2 m9 rfu rfu rfu b2 r-lb# d4 rfu rfu a1 rfu rfu b9 rfu rfu b10 rfu rfu rfu rfu rfu rfu rfu p2 rfu r1-ce2 e6 r-v ccq m7 e4 r-ub# n9 p9 p10 n10 n1 n2 p1 r-vcc l2 l 2 l2 a1 g2 g2 a4 g3 g3 a17 g4 g4 a23 g6 g6 a10 g7 g7 a14 g8 g8 a22 g9 g9 a9 a10 b1 a2 wp#/acc f2-ce# f2-oe# f3-ce# d9 f-rst# ry/by# f1-ce# legend: xram shared psram only flash/xram shared flash/data shared rfu (reserved for future use) code flash only x mirrorbit data only x x x k8 k8 dq7 k9 k9 vss k7 k7 dq12 k4 k4 dq10 k3 k3 dq0 k6 r1-v cc k2 r1-ce1# f-vcc wp#/acc l9 f-v cc f4-ce# m6 f-v ccq x x x x x x x x x x x d5 d5 c5 c5 c9 c9 e5 e5 f5 f5 j2 j2 k5 k5 m5 m5 m8 m8 r2-ce1# g5 g5 h5 h5 r2-v cc h6 h6 r2-ce2
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 15 advance information /7/7! 34"1(-9(!)*!34 figure 4.7 connection diagram C 56-pin tsop (s29pl256n) /7/7 34"1(-9(!)*+!e
(!)*+!) figure 4.8 connection diagram C 56-pin tsop ( (s29pl127n and s29pl129n)) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc nc nc dq 15 dq 7 dq 14 dq 6 v ssq v io dq 13 dq 5 dq 12 dq 4 v cc v ss dq 11 dq 3 dq 10 dq 2 v ccq v ssq 34 33 32 31 30 29 dq 9 dq 1 dq 8 dq 0 oe # ce# a 22 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 a 23 a 21 a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 we# reset# acc/wp# ry/by 56-pin tsop top view marking side 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc nc nc dq 15 dq 7 dq 14 dq 6 v ss v io (v ccq ) dq 13 dq 5 dq 12 dq 4 v cc v ss dq 11 dq 3 dq 10 dq 2 v io (v ccq ) v ss 34 33 32 31 30 29 dq 9 dq 1 dq 8 dq 0 oe # ce1# a 22 (pl127n), nc (pl129n) a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 nc(pl127n), ce2# (pl129n) a 21 a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 reset# acc/wp# ry/by# 56-pin tsop top view marking side we#
16 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information /7/7/ %
d1(.1( 634 figure 4.9 physical dimensions C 56-pin tsop (s29pl256n) 6 2 3 4 5 7 8 9 ts/tsr 056 mo-142 (d) ec 56 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 13.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 14.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 14.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n + 1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b 3356 \ 16-038.10 c
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 17 advance information
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 18 advance information 5 additional resources 0
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 19 advance information 6 product overview 67 )))/ 6<= :6;4$!89" !

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table 6.1 s29pl256n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes h 4g h =h 99 999999"99>,,, a - =h 9: 99;999"99,,,, =h 96 9:9999"9:>,,, =h 98 9:;999"9:,,,, :< 6<= 9h 969999"98,,,, " - * + s s s 6<= 9:; :-9999":,,,,, g :64g h; 6<= :7 699999"6:,,,, , ! " ! - * + s s s 6<= == >-9999">,,,,, :64g h; 6<= => ;99999";:,,,, , ! " ! - * + s s s 6<= ::h -9999",,,,, h4g :< 6<= ::< -99999"-:,,,, " - * + s s s 6<= :67 ,9999",,,,, h =h :89 ,-9999",->,,, " - =h :8: ,-;999",-,,,, =h :86 ,,9999",,>,,, =h :88 ,,;999",,,,,,
20 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information >

table 6.2 s29pl127n/s29pl129n sector and memory address map bank bank size sector count sector size (kb) sector/ sector range address range notes 64g h =h 99 999999"99>,,, " - =h 9: 99;999"99,,,, =h 96 9:9999"9:>,,, =h 98 9:;999"9:,,,, > 6<= 9h 969999"98,,,, a - * + s s s 6<= :9 9-9999"9,,,,, g =4g 6h 6<= :: :99999"::,,,, , ! " ! - * + s s s 6<= 8h 8-9999"8,,,,, =4g 6h 6<= 8< h99999"h:,,,, , ! " ! - * + s s s 6<= <; =-9999"=,,,,, 64g > 6<= <7 >99999">:,,,, " - * + s s s 6<= =< >9999">,,,, h =h == >-9999">->,,, " - =h => >-;9999">-,,,, =h =; >,9999">,>,,, =h =7 >,;999">,,,,, table 6.3 pl129n sector and memory address map bank bank size sector count sector size (kb) ce1# ce2# sector/ sector range address range notes : 64g h =h 0 0 2 99 999999"99>,,, " - =h 9: 99;999"99,,,, =h 96 9:9999"9:>,,, =h 98 9:;999"9:,,,, > 6<= 9h 969999"98,,,, a - * + s s s 6<= :9 9-9999"9,,,,, :g =4g 6h 6<= :: :99999"::,,,, , ! " ! - * + s s s 6<= 8h 8-9999"8,,,,, 6 =4g 6h 6<= 0 2 0 8< h99999"h:,,,, , ! " ! - * + s s s 6<= <; =-9999"=,,,,, 6g 64g > 6<= <7 >99999">:,,,, " - * + s s s 6<= =< >9999">,,,, h =h == >-9999">->,,, " - =h => >-;9999">-,,,, =h =; >,9999">,>,,, =h =7 >,;999">,,,,,
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 21 advance information 7 device operations $!!!

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7.1 device operation table
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table 7.1 device operation operation ce# oe# we# reset# wp#/acc addresses (a max C a0) dq15 C dq0 i 2 2 t / 1d . 2 2 t * / + / / $ 2 t t 2 t / 2"c 1

$ 2 2 2 t / 2"c i t t t t / 2"c
22 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information
64664 *6 d46d4 *d *b4!!e! dd 4.e= @4bf
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$ > 8 table 7.2 dual chip enable device operation operation ce1# ce2# oe# we# reset# wp#/acc addresses (a21 C a0) dq15 C dq0 i 2 2 2 t / 1d 2 . 2 2 2 t * /6 + / / 2 $ 2 2 t t 2 t t 2"c 1

$ 2 2 2 t t 2"c i t t t t t t 2"c d *20+ tttt 0 t / /
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 23 advance information
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+ table 7.3 word selection within a page word a2 a1 a0 .9 9 9 9 .: 9 9 : .6 9 : 9 .8 9 : : .h : 9 9 .< : 9 : .= : : 9 .> : : :
24 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information $ : 6 : #

64664 *6 d46d4 *d ')4'#)
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table 7.4 autoselect codes description ce# see note oe# we# a max C a12 a10 a9 a8 a7 a6 a5 C a4 a3 a2 a1 a0 dq15 to dq0 4

2 g t t t t 999: & i : 2 gttt 2 66>- i 6 222 668* 6<=/+ 6669* :6>/+ 666:* :67/+ i 8 2222 6699* 6<=/+ 6699* :6>/+ 6699* :67/+ 0 2ttt2 9999 d */fg g +! 999: *-fg g + g 2 g t t t 2 2 " 3:<"3;l9 " 3>", g :l !9l/ " 3="
g :l !9l/ " 3<"2 g :li! 9l 2 " 3hv38" . ? g 99l. ? $g gg ! ::l/. ? " 36"39l9 software functions and sample code table 7.5 autoselect entry *,
lw
- + cycle operation byte address word address data d : . g) g)<<< 9)99 d 6 . g)<<< g)6 9)99<<
. g) g)<<< 9)9979 table 7.6 autoselect exit *,
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-)+ cycle operation byte address word address data d : . $o))) $o))) 9)99,9
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 25 advance information /* here is an example of autoselect mode (getting manufacturer id) */ /* define uint16 example: typedef unsigned short uint16; */ uint16 manuf_id; /* auto select entry */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0090; /* write autoselect command */ /* multiple reads can be performed after entry */ manuf_id = *((uint16 *)bank_addr + 0x000); /* read manuf. id */ /* autoselect exit */ *((uint16 *)base_addr + 0x000) = 0x00f0; /* exit autoselect (write reset command) */
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 26 advance information 7.4 program/erase operations $ $
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27 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information figure 7.1 single word program operation '4')

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/* example: program command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll for program completion */ software functions and sample code ta b l e 7 . 7 s i n g l e wo r d p r o g r a m *,
lw + cycle operation byte address word address data d : . go go<<< 99 d 6 . g o< . go go<<< 999 . . . . write unlock cycles: address 555h, data aah address 2aah, data 55h write program command: address 555h, data a0h program data to address: pa, pd unlock cycle 1 unlock cycle 2 setup command program address (pa), program data (pd) fail. issue reset command to return to read array mode. perform polling algorithm (see write operation status flowchart) yes yes no no polling status = busy? polling status = done? error condition (exceeded timing limits) pass. device is in read mode.
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 28 advance information e7/7! #$
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 30 advance information
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/* example: write buffer programming command */ /* notes: write buffer programming limited to 16 words. */ /* all addresses to be written to the flash in */ /* one operation must be within the same flash */ /* page. a flash page begins at addresses */ /* evenly divisible by 0x20. */ uint16 *src = source_of_data; /* address of source data */ uint16 *dst = destination_of_data; /* flash destination address */ uint16 wc = words_to_program -1; /* word count (minus 1) */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)sector_address) = 0x0025; /* write write buffer load command */ *((uint16 *)sector_address) = wc; /* write word count (minus 1) */ loop: *dst = *src; /* all dst must be same page */ /* write source data to destination */ dst++; /* increment destination pointer */ src++; /* increment source pointer */ if (wc == 0) goto confirm /* done when word count equals zero */ wc--; /* decrement word count */ goto loop; /* do it again */ confirm: *((uint16 *)sector_address) = 0x0029; /* write confirm command */ /* poll for completion */ /* example: write buffer abort reset */ *((uint16 *)addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)addr + 0x555) = 0x00f0; /* write buffer abort reset */
31 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information figure 7.2 write buffer programming operation e7/7 ('

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* - + write unlock cycles: address 555h, data aah address 2aah, data 55h issue write buffer load command: address 555h, data 25h load word count to program program data to address: sa = wc unlock cycle 1 unlock cycle 2 wc = number of words ? 1 yes yes yes yes yes no no no no no wc = 0? write buffer abort desired? write buffer abort? polling status = done? error? fail. issue reset command to return to read array mode. write to a different sector address to cause write buffer abort pass. device is in read mode. confirm command: sa 29h wait 4 s perform polling algorithm (see write operation status flowchart) write next word, decrement wc: pa data , wc = wc ? 1 reset. issue write buffer abort reset command
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 32 advance information $ --

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/* example: sector erase command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)sector_address) = 0x0030; /* write sector erase command */ software functions and sample code ta b l e 7 . 9 s e c t o r e r a s e *,
lw -+ cycle description operation byte address word address data : d . go go<<< 99 6 d . go< . go go<<< 99;9 h d . go go<<< 99 < d . go<

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33 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information ! % $ !!

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no write unlock cycles: address 555h, data aah address 2aah, data 55h write sector erase cycles: address 555h, data 80h address 555h, data aah address 2aah, data 55h sector address, data 30h write additional sector addresses fail. write reset command to return to reading array. pass. device returns to reading array. wait 4 s perform write operation status algorithm select additional sectors? unlock cycle 1 unlock cycle 2 yes yes yes yes yes no no no no last sector selected? done? dq5 = 1? command cycle 1 command cycle 2 command cycle 3 specify first sector for erasure error condition (exceeded timing limits) status may be obtained by reading dq7, dq6 and/or dq2. poll dq3. dq3 = 1? ? each additional cycle must be written within t sea timeout ? timeout resets after each additional cycle is written ? the host system may monitor dq3 or wait t sea to ensure acceptance of erase commands ? no limit on number of sectors ? commands other than erase suspend or selecting additional sectors for erasure during timeout reset device to reading array data
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 34 advance information . -$- !$
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/* example: chip erase command */ /* note: cannot be suspended */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0080; /* write setup command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write additional unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write additional unlock cycle 2 */ *((uint16 *)base_addr + 0x000) = 0x0010; /* write chip erase command */ e7/73 '
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lw-+ cycle description operation byte address word address data : d . go go<<< 99 6 d . go< . go go<<< 99;9 h d . go go<<< 99 < d . go< 35 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information "
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/* example: erase suspend command */ *((uint16 *)bank_addr + 0x000) = 0x00b0; /* write suspend command */
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/* example: erase resume command */ *((uint16 *)bank_addr + 0x000) = 0x0030; /* write resume command */ /* the flash needs adequate time in the resume state */ e7/74
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 36 advance information i
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37 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information
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/* example: unlock bypass entry command */ *((uint16 *)bank_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)bank_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)bank_addr + 0x555) = 0x0020; /* write unlock bypass command */ /* at this point, programming only takes two write cycles. */ /* once you enter unlock bypass mode, do a series of like */ /* operations (programming or sector erase) and then exit */ /* unlock bypass mode before beginning a different type of */ /* operations. */ /* example: unlock bypass program command */ /* do while in unlock bypass entry mode! */ *((uint16 *)bank_addr + 0x555) = 0x00a0; /* write program setup command */ *((uint16 *)pa) = data; /* write data to be programmed */ /* poll until done or error. */ /* if done and more to program, */ /* do above two cycles again. */ software functions and sample code table 7.15 unlock bypass entry *,
lwd g- + cycle description operation byte address word address data : d . go go<<< 99 6 d . go< lwd g + cycle description operation byte address word address data :
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 38 advance information /* example: unlock bypass exit command */ *( (uint16 *)base_addr + 0x000 ) = 0x0090; *( (uint16 *)base_addr + 0x000 ) = 0x0000; e7/7) #-&
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lwd gi+ cycle description operation byte address word address data : i : . go))) go))) 9979 6 i 6 . go))) go))) 9999
39 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information figure 7.4 write operation status flowchart start read 1 dq7=valid data? yes no read 1 dq5=1? yes no write buffer programming? yes no device busy, re-poll read3 dq1=1? yes no read 2 read 3 read 2 read 3 read 2 read 3 read3 dq1=1 and dq7 valid data? yes no (note 4) write buffer operation failed dq6 toggling? yes no timeout (note 1) (note 3) programming operation? dq6 toggling? yes no yes no dq2 toggling? yes no erase operation complete device in erase/suspend mode program operation failed device error erase operation complete read3= valid data? yes no notes: 1. dq6 is toggling if read2 dq6 does not equal read3 dq6. 2. dq2 is toggling if read2 dq2 does not equal read3 dq2. 3. may be due to an attempt to program a 0 to 1. use the reset command to exit operation. 4. write buffer error if dq1 of last read =1. 5. invalid state, use reset command to exit operation. 6. valid data is the data that is intended to be programmed or all 1's for an erase operation. 7. data polling algorithm valid for all operations except advanced sector protection. device busy, re-poll device busy, re-poll device busy, re-poll (note 1) (note 2) (note 6) (note 5)
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 40 advance information
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41 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information
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43 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 7.5 simultaneous read/write

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) 3 4)-567,0)-56!8,0 figure 7.5 simultaneous operation block diagram for s29pl256n and s29pl127n v cc v ss bank a address bank b address a max ? a0 reset# we# ce# dq0 ? dq15 state control and command register ry/by# bank a x-decoder oe# dq15 ? dq0 status control a max ?a0 a max ? a0 a max ? a0 a max ?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank b x-decoder y-gate bank c x-decoder bank d x-decoder y-gate bank c address bank d address wp#/acc v io
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 44 advance information figure 7.6 simultaneous operation block diagram for s29pl129n v cc v ss bank 1a address bank 1b address a21 ? a0 reset# we# ce1# dq0 ? dq15 ce2# state control and command register ry/by# bank 1a x-decoder oe# status control a21 ? a0 a21 ? a0 a21 ? a0 a21 ? a0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 dq15 ? dq0 mux mux mux bank 1b x-decoder y-gate bank 2a x-decoder bank 2b x-decoder y-gate bank 2a address bank 2b address ce1# = l ce2# = h ce1# = h ce2# = l wp#/acc
45 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 7.6 writing commands /command sequences
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 46 advance information 7.7 hardware reset i--?
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 48 advance information 8 advanced sector protection/unprotection bd
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;: figure 8.1 advanced sector protection/unprotection hardware methods software methods wp# = v il (all boot sectors locked) password method (dq2) persistent method (dq1) lock register (one time programmable) ppb lock bit ( notes 1, 2, 3 ) 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n (note 4) ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppd) ( notes 5, 6 ) dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) (notes 7, 8, 9) notes: 1. bit is volatile, and defaults to 1 on reset. 2. programming to 0 locks all ppbs to their current state. 3. once programmed to 0, requires hardware reset to unlock. 4. n = highest address sector. 5. 0 = sector protected, 1 = sector unprotected. 6. ppbs programmed individually, but cleared collectively. 7. 0 = sector protected, 1 = sector unprotected. 8. protect effective only if ppb lock bit is unlocked and corresponding ppb is 1 (unprotected). 9. volatile bits: defaults to user choice upon power-up (see ordering options).
49 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 8.1 lock register !
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51 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information : / #

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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 52 advance information figure 8.2 lock register program algorithm write unlock cycles: address 555h, data aah address 2aah, data 55h write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 77h*, data pd unlock cycle 1 unlock cycle 2 xxxh = address don?t care * not on future devices program data (pd): see text for lock register definitions caution: lock data may only be progammed once. wait 4 s pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. perform polling algorithm (see write operation status flowchart) yes yes no no done? dq5 = 1? error condition (exceeded timing limits) fail. write rest command to return to reading array.
53 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 8.6 advanced sector protection software examples $ ; 6 $ $ fg! g! g g "

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0 0 e1 table 8.2 sector protection schemes unique device ppb lock bit 0 = locked, 1 = unlocked sector ppb 0 = protected 1 = unprotected sector dyb 0 = protected 1 = unprotected sector protection status 9 9 )
g 9 9 )
g 9 : : d 9 : 9
fg : 9 )
g : 9 )
g : : 9
fg : : : d
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 54 advance information >7e7 # 0 +$ /
8 * + 1-? !-?.-? >7e7/ ,"c&#% .-?l-?li--?l0 1-?l0 2

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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 55 advance information 9 power conservation modes 9.1 standby mode . ! $ !

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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 56 advance information 10 secured silicon sect or flash memory region
), $
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table 10.1 secured silicon sector addresses sector sector size address range
:6; 9999;9"9999,, , :6; 999999"9999>,
57 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 10.2 customer secured silicon sector

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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 58 advance information '4')
/* example: secsi sector entry command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0088; /* write secsi sector entry cmd */ '4')
/* once in the secsi sector mode, you program */ /* words using the programming algorithm. */ '4')
/* example: secsi sector exit command */ *((uint16 *)base_addr + 0x555) = 0x00aa; /* write unlock cycle 1 */ *((uint16 *)base_addr + 0x2aa) = 0x0055; /* write unlock cycle 2 */ *((uint16 *)base_addr + 0x555) = 0x0090; /* write secsi sector exit cycle 3 */ *((uint16 *)base_addr + 0x000) = 0x0000; /* write secsi sector exit cycle 4 */ table 10.2 secured silicon sector entry *,
lw - + cycle operation byte address word address data d : . g o go<<< 99 d 6 . go< lw + cycle operation byte address word address data d : . g o go<<< 99 d 6 . go< . go go<<< 999 . . . . table 10.4 secured silicon sector exit *,
lw -)+ cycle operation byte address word address data d : . g o go<<< 99 d 6 . go< august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 59 advance information 11 electrical specifications 11.1 absolute maximum ratings
a= a= &
b1) $* /: + a9<00 1 o9<0 0 * /: + a9<0oh90 0 1 * /: + a9<0oh90 * /6 + a9<0o:9<0 1

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60 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 11.2 operating ranges # # $
* + a6 $
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0 o6> 08: 0 o89 0o8= 0 * /8 + 0 1
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11.3 test conditions figure 11.3 te s t s e t u p table 11.1 test specifications test condition all speeds unit 1

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i , 0 1 l:;0 < 0 1 l890

0 1 l:;0 99":; 0 0 1 l890 99a89

0 1 b6 0 1

0 1 b6 0 c l device under test
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 61 advance information 11.4 key to switching waveforms 11.5 switching waveforms figure 11.4 input waveforms and measurement levels 11.6 v cc power up !

3 ! ;am n4 */ e!

figure 11.5 v cc power-up diagram waveform inputs outputs 2 2 y! !d / 2 *2c+ parameter description test setup speed unit 0 0
4 : 01 0 1
4 89 j i- $ i--? -? 4 699 v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs v cc v io reset# t vcs t vios t read ce# v cc min v io min v ih
62 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 11.7 dc characteristics ++7e7+%

2 j!7e2 742 5-(&
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56!=, parameter symbol parameter description (notes) test conditions min * /6 ) ty p * /6 ) max unit

0 / l0 0 !0 l0 ) * = +x69j 1 1

0 1d l0 0 !1-?l0 2 0 l0 ) * = + x:9 j : 0 i
* : ! 8 + 1-?l0 2 ! 0 l0 ) * : ! = + <42% 89 h< :942% =9 79 6 0 .
* 8 + 1-?l0 2 !.-?l0 6< <9 8 0 $
-?* ; +!i--?! . ?bl0 1 980 69 h9 j h 0 i
i--?l0 980 6 <9 j <
4* h +0 2 l0 1 980m0 l0 980 69 h9 j = 0 i".".
* : + 1-?l0 2 <42% 8< <9 :942% =< 7< > 0 "."-"

* < + 1-?l0 2 6> << ; 0 i
1-?l0 2 !; i h942% =:9 0
0 0 1 l:=<:7<0 a9h 9h 0 0 1 l6>8=0 a9< 9; 0 0 2
20 0 1 l:=<:7<0 0 1 a9h 0 1 o9h 0 0 1 l6>8=0 69 0 o98 0 0 22 0 0 l890x:9z* = +;<7<0 0 1 1

0 1 l:99j!0 l0 * = + 0 1 l0 9: 0 0 12 1

20 12 la:99j* = + 0 1 l0 0 a96 * > + 0 0 e1 0 "1
0* < +686<0
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 63 advance information ++7e7!%

2 j!7e2 7+2 5-(&
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0 / l0 0 !0 l0 ) * = +x6j 1 1

0 1d l0 0 !1-?l0 2 0 l0 ) * = + x: j : 0 i
* : ! 6 + 1-?l0 2 ! 0 l0 ) * : ! = + <42% 6; h9 :942% <; >< 6 0 .
* 6 ! 8 + 1-?l0 2 !.-?l0 66 h9 8 0 $
* 6 + -?* ; +!i--?!. ?b l0 1 980 69 h9 j h 0 i
* 6 +i--?l0 980 6 <9 j <
4* 6 ! h +0 2 l0 1 980m0 l0 9:0 69 h9 j = 0 i".".
* : ! 6 + 1-?l0 2 <42% 88 h< :942% =8 ;9 > 0 "."-"

* 6 ! < + 1-?l0 2 6h h< ; 0 i
* 6 + 1-?l0 2 ! ; i h942% = 7 0
0 0 1 l:=<:7<0 a9h 9h 0 0 1 l6>8=0 a9< 9; 0 0 2
20 0 1 l:=<:7<0 0 1 a9h 0 1 o9h 0 0 1 l6>8=0 69 0 o98 0 0 22 0 0 l890x:9z* = +;<7<0 0 1 1

0 1 l:99j!0 l0 * = + 0 1 l0 9: 0 0 12 1

20 12 la:99j* = + 0 1 l0 0 a96 * > + 0 0 e1 0 "1
0* < +686<0
64 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information 11.8 ac characteristics ++7>7+
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figure 11.6 read operation timings parameter description (notes) test setup speed options jedec std. 60 65 70 unit 00 i i * : + 4 =9 =< >9 030 1

-?!1-?l0 4) =9 =< >9 -30 - - $1

* < + 1-?l0 4) =9 =< >9 4) 6< 89 89 k30 1- 1

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- $ 2* : + i 4 9 ? 4 :9 t oh t ce data we# addresses ce# oe# high z valid data high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 65 advance information figure 11.7 page read operation timings ++7>7 =
,
'('1: ,!p figure 11.8 reset timings parameter description all speed options unit jedec std. i i--?
. 4 89 j i2 i2gi* / +4 699 same page addresses a 22 to a 3 output t ce t acc aa aa+1 aa+2 aa+3 aa+4 aa+5 aa+6 aa+7 t oe t oeh t pacc high-z t oh da da+1 da+2 da+7 t df da+3 da+4 da+5 da+6 t oh t oh t oh t oh t oh t oh t oh t pacc t pacc t pacc t pacc t pacc t pacc a 2 to a 0 ce# oe# we# reset# t rp ce#, oe# t rh
66 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information ++7>7/'
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description (notes) speed options unit r-- 60 65 70 00 . . * : + 4 =9 =< >9 0.
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.2 4 6< ib. g i .1 4 9 .2.2: .2.2: 1 h9 j .2.2: .2.2: 1 6h j .2.26 .2.26 -1 := 022 0 22 i , 4 6<9 ig .i ifbgf? 4 9 gdf b-0ifbgf? 4) 79 .- /
4 .-? 4) 8 - - "
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 67 advance information 5)4

5b4

b /g

figure 11.9 program operation timings figure 11.10 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
68 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information %)4

-
%
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0 )4 )

- h
/
% 0 figure 11.11 chip/sector erase operation timings figure 11.12 back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch status d out t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t as t rc t ce t ah valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t as
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 69 advance information )4
*

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figure 11.13 data# polling timings (during embedded algorithms) )4
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figure 11.14 toggle bit timings (during embedded algorithms) we# ce# oe# high z t oe high z dq7 dq6?q0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
70 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information bi

c
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parameter (notes) device condition ty p ( note 1 ) max ( note 2 ) unit comments (notes) - :6;e 0 := > -)
99
* h + := > 86e 0 98 h 98 h - 0 696* 6<=/+ :99* :6>/+ :99* :67/+ g* 6<=/+ g* :6>/+ g* :67/+ :89* 6<=/+ =<* :6>/+ =<* :67/+ g* 6<=/+ g* :6>/+ g* :67/+ . 0 h9 h99 j -)
* < + 6h 6h9 - .
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0 7h 7h j = =9 86".g
0 899 8999 j :76 :769
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* 8 + 0 :<>8* 6<=/+ >;=* :6>/+ >;=* :67/+ 8:<* 6<=/+ :<;* :6>/+ :<;* :67/+ -)
* < + :99* 6<=/+ <9* :6>/+ <9* :67/+ 699* 6<=/+ :99* :6>/+ :99* :67/+ -
b-i
[69 j
b i
[69 j enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 71 advance information ++7>74$a$

&

! % !p ) 44!+do parameter symbol parameter description test setup typ max unit /
0 / l9 > :9 , 1d 1

0 1d l9 ; :6 , /6 0 / l9 ; :: ,
august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 72 advance information 12 appendix , , ! i
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table 12.1 memory array commands command sequence (notes) cycles bus cycles (notes 1 C 6 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data i* > +:ii i* ; +:ttt,9
" * 7 + 4

h <<< 6 << \g]<<< 79 \g]t99 999: * :9 + = <<< 6 << \g]<<< 79 \g]t9: 66>- \g]t9- * / :9 + \g]t9, 6699 g h <<< 6 << \g]<<< 79 \g]t98 * / :: + h <<< 6 << <<< 9 .g
* :> + = <<< 6 << 6< . .g g
, : 67 .g
$i* :> + 8 <<< 6 << <<< ,9 - = <<< 6 << <<< ;9 <<< 6 << <<< :9 - = <<< 6 << <<< ;9 <<< 6 << 89 b-
* :h + : g g9 b-i
* :< +:g89 ,3
* := + : \g]<<< 7; d g 4 d g- 8 <<< 6 << <<< 69 d g * :6 ! :8 +6tt9 d g -* :6 ! :8 +6 tt ;9 89 d g-* :6 ! :8 + 6 tt ;9 ttt :9 d g,* :6 ! :8 +:g7; d gi 6 tt 79 ttt 99

- * :; + 8 <<< 6 << <<< ;;
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73 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information table 12.2 sector protection commands command sequence (notes) cycles bus cycles (notes 1 C 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data i i i - * 6< + 8 <<< 6 << <<< h9 ig * 6= + 6tt 9 99 igi :99 i -)* 6> + 6tt 79 tt 99 - * 6< + 8 <<< 6 << <<< =9 6tt 9 99b9: 96b98 .9b .:b .6b .8 i h 99 .9 9: .: 96 .6 98 .8 d > 99 6< 99 98 99 .99: .: 96 .698 .899 67 -)* 6> + 6tt 79 tt 99 / "0 g / "0 - * 6< + 8 <<< 6 << \g]<<< 9 g 6tt 9\g]99 g-* 66 + 6tt ;9 99 89 g
i :\g]i*9+ / "0 -)* 6> + 6tt 79 tt 99 k$/ "0 ,% g g k$0 ,% - * 6< + 8 <<< 6 << <<< <9 g g 6tt 9 tt 99 g g
i :gi*9+ k$0 ,% -)* 6> + 6tt 79 tt 99 0 fg 0 - * 6< + 8 <<< 6 << \g]<<< -9 fg 6tt 9\g]99 fg 6tt 9\g]9: fg
i :\g]i*9+ 0 -)* 6> + 6tt 79 tt 99 !8 &
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august 8, 2005 s29pl-n_00_a1 s29pl-n mirrorbit? flash family 74 advance information 12.1 common flash memory interface , *,+
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/* example: cfi entry command */ *((uint16 *)bank_addr + 0x555) = 0x0098; /* write cfi entry command */ /* example: cfi exit command */ *((uint16 *)bank_addr + 0x000) = 0x00f0; /* write cfi exit command */ ! %- $ 8! 0

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75 s29pl-n mirrorbit? flash family s29pl-n_00_a1 august 8, 2005 advance information ,
!, *r--
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table 12.3 cfi query identification string addresses data description :9 :: :6 99<: 99<6 99<7 3
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colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reac tion control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile lau nch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above- mentioned uses of the products. any semiconductor device has an inherent chance of failure. you must protect against injury, da mage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan , the us export administration regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves th e right to change or discontinue work on any product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2005 spansion llc. all rights reserved. spansion, the sp ansion logo, and mirrorbit are trademarks of spansion llc. o ther company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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